As explained with reference to FIGS. 1-3C, signal line drivers are susceptible to unwanted transmissions of shoot-through current. The problem occurs in, among other circuits, CMOS imaging devices, because resulting current spikes can produce noise within captured images. Accordingly, the embodiments of the invention are disclosed with reference to, but are not limited to, use in a CMOS imaging device.
FIG. 1 is a circuit diagram illustrating a non-limiting example of a conventional four transistor pixel cell 150, which may be used in a CMOS imaging device. During an integration period, light strikes the photosensor 101 and generates charges stored in an accumulation region of the photosensor. After the integration period and in response to a charge transfer signal TX, a charge transfer transistor 106 gates the photogenerated charges from the accumulation region to a storage node 102, which may be constructed as a floating diffusion region. The transferred charges bias the gate of a source follower transistor 108, which has a first terminal connected to a voltage source VDD and a second terminal that consequently transmits an image signal Vsig indicating the amount of charge stored in the storage node 102. In response to a row select signal ROW, a row select transistor 109 gates the image signal Vsig to a column line 160 for subsequent sampling and processing. The pixel cell actually generates two output voltage signals, one is a reset signal Vrst, which is produced by transistor 108 when the storage node 102 is reset to a predetermined charge level by an “on” state of reset transistor 107, and the other is the image signal Vsig.
FIG. 2 is a block diagram illustrating a non-limiting example of a conventional CMOS imaging device 200 for reading out a captured image, as digital data, to an image processor 280. The imaging device 200 includes a pixel array 260 having a plurality of pixel cells 150 arranged in rows and columns, and row 170 and column 120 drivers for accessing the pixel cells to control their operation during signal readout. In CMOS images with larger pixel arrays, the pixel rows may be accessed by devices provided to drive control signal lines on both the left and right sides of the array, as shown in FIG. 2. Thus, in response to row address signals ADD (not shown) from left and right row address decoders 110L, 110R (hereinafter also collectively referred to as row address decoders 110), respective left and right row drivers 170L, 170R (hereinafter also collectively referred to as row drivers 170) selectively transmit charge transfer TX, reset RST, and row select ROW signals to the charge transfer 106, reset 107, and row select 109 transistors of the pixel cell 150 of an addressed pixel row. The transistors 106-109 within the each pixel row are thereby controlled to generate the output signals Vrst, Vsig of the pixel cells 150 within the addressed pixel row, and to provide the output signals to respective column lines 160 connected to the pixel cells 150. In response to a column address signal COL (not shown) from a column address decoder 270, a column driver 120 gates each of the output signals Vrst, Vsig from their respective column lines 160 to a sample and hold (S/H) circuit 265, which samples and holds the Vrst, Vsig signals. A timing and control circuit 250 controls the row and column address decoders 110, 270 to coordinate the generation and readout of the output signals by the pixel cells 150.
At respective times, the reset Vrst and image Vsig signals of the pixel cell 150 are provided by the row select transistor 109 to the respective column line 160, and then provided by the column driver 120 to respective capacitors of the S/H circuit 265. The held reset Vrst and image Vsig signals are converted to a differential signal (Vrst−Vsig) by a differential amplifier 267. The differential signal (Vrst−Vsig) is converted to digital data by an analog-to-digital converter (ADC) 275, and the digital data is provided to the image processor 280 for processing with the digital data of other pixel cells 150 of the pixel array 200.
FIG. 3A is a block diagram illustrating a non-limiting example of a dual row driver architecture 300, which may be employed by the imaging device 200 of FIG. 2. For convenience, only two pixel rows and two pixel cells 150 (of each row) are illustrated. As shown, the left and right row drivers 170L, 170R collectively provide three pairs of row driver buffers to each pixel row: left and right reset signal buffers 340L(RST), 340R(RST) for driving a shared reset signal line 130(RST); left and right row select signal buffers 340L(ROW), 340R(ROW) for driving a shared row select signal line 130(ROW); and left and right charge transfer signal buffers 340L(TX), 340R(TX) for driving a shared charge transfer signal line 130(TX) (hereinafter also collectively referred to as buffers 340(RST), 340(ROW), 340(TX), 340L, 340R, and 340). Each set of left and right buffers 340L, 340R drives either the reset 107, row select 109, or charge transfer 106 transistors of a pixel row by selectively transmitting “high” and “low” signal outputs to a respective signal line 130; e.g., the left and right reset signal buffers 340L(RST), 340R(RST) control the reset transistors 107 of the illustrated pixel row by concurrently transmitting a high or low signal output to the reset signal line 130(RST).
By using left and right buffers 340L, 340R to drive opposing ends of a shared signal line 130, the dual row driver architecture 300 reduces signal propagation delay. In a single row driver architecture having only one signal line driver per signal line 130, a transmitted signal has a maximum propagation delay Tmax of approximately:Tmax=½RC  (1)where R and C are the total resistance and capacitance, respectively, of the signal line 130 from the start point to the end point of transmission. In the dual row driver architecture 300, a signal has a maximum propagation delay Tmax of approximately:Tmax=⅛RC  (2)because the total resistance R and total capacitance C are each reduced by about one-half.
The dual row driver architecture 300 is susceptible to “inter” shoot-through current when the left and right buffers 340L, 340R are not operated in perfect synchronism and thus transmit different signal outputs at the same time. Even if the buffers 340L, 340R are designed to simultaneously switch between their high and low signal outputs, that may not always be the case. When one of the opposing buffers 340L, 340R lags behind the other in switching from a high to a low signal output, or vice-versa, inter shoot-through current can short across the signal line 130 from the high voltage source (e.g., a VDD output terminal) of the buffer 340 driving the signal line 130 high to the low voltage source (e.g., a VSS or GND output terminal) of the buffer 340 concurrently driving the signal line 130 low.
Each of the buffers 340L, 340R is also susceptible to “intra” shoot-through current. Intra shoot-through current occurs when an individual buffer 340 transmits both a high and low signal output to the signal line 130 at the same time. As will be further explained below, each of the buffers 340 selectively drives the signal line “high” and “low” by gating a high voltage signal from a high voltage source (e.g., a VDD output terminal) to the signal line 130; and by gating a low voltage signal from a low voltage source (e.g., a VSS or GND) to the signal line 130. If a buffer 340 concurrently provides the high and low voltage sources access to the signal line 130 (or to a common output node), the high and low voltage sources are temporarily connected and intra shoot-through current can transmit between them within the buffer 340. Because intra shoot-through current occurs within a single buffer 340, it can occur in single and dual row driver architectures alike.